1. Field of the Invention
The present invention relates generally to computational systems and, more particularly, to architectural techniques for instruction set processors.
2. Description of the Related Art
Processor architects have long sought to implement instruction set architectures using techniques that need not directly support some instructions in hardware. Indeed, modem processors often provide facilities whereby at least some instructions, when presented in an instruction sequence, are not directly executed but are instead presented to processor logic as operations (or operation sequences) that correspond to instructions defined by an instruction set architecture (ISA). In some cases, such lower-level operations are referred to as microinstructions, μops, helper instructions or simply, microcode.
Indeed, microcoding techniques were commonly used in early IBM mainframe processors to provide a range of implementations of a given instruction set architecture in which functionality corresponding to certain instructions might be supported in lower-end implementations using microcode, whereas higher-end implementations might directly implement the corresponding instructions in hardware. Microprogramming techniques have also been commonly employed in an effort to maintain instruction set compatibility with legacy instruction sets while incorporating advances in computer architecture in the underlying hardware. Superscalar implementations of x86 (or IA-32) instruction set architectures are a prime example of this design technique. In some cases, few (if any) individual instructions (or operations) implemented by the underlying hardware may precisely correspond to actual instruction set instructions. Classic examples include those processor architectures that employ an underlying RISC-style core to implement a CISC-style instruction set. Many commercially-available processors, including those available from Sun Microsystems, Inc., Advanced Micro Devices, Intel, IBM, Motorola, etc. may employ techniques such as described above.
Unfortunately, while microcoding techniques allow a degree of decoupling between underlying hardware mechanisms and the functionality defined by an instruction set that (unlike the underlying hardware) tends to remain vital for multiple generations, many basics aspects of microcoding techniques have remained relatively unchanged for years. Typically, a fixed set of instruction set instructions (including, in some processors, the set of all instruction set instructions) is handled using a microcode store and sequencer. Typically, in those processor implementations in which less than all ISA instructions are microcoded, a given instruction is either directly supported or microcoded and typically either or both the underlying microcode and any mapping of instruction set instructions to microcode is (are) static.
As underlying hardware itself becomes increasingly complex and as concurrent and speculative execution techniques add to this complexity, additional flexibility may be desirable at the interface between instruction set and implementation.